1. Field of the Invention
The present invention relates generally to semiconductor structures and manufacturing. More particularly, the invention relates to extremely thin dielectric layers and the formation thereof.
2. Background
Advances in semiconductor manufacturing technology have led to the integration of millions of circuit elements, such as transistors, on a single integrated circuit (IC). In order to integrate increasing numbers of circuit elements onto an integrated circuit it has been necessary to reduce the line widths of the various parts that make up an integrated circuit. Not only have interconnect line widths become smaller, but so have the dimensions of metal-oxide-semiconductor field effect transistors (MOSFETs).
MOSFETs are also sometimes referred to as insulated gate field effect transistors (IGFETs). Most commonly, these devices are referred to simply as FETs, and are so referred to in this disclosure.
Transistor scaling typically involves more than just the linear reduction of the FET width and length. For example, both source/drain (S/D) junction depth and gate dielectric thickness are also typically reduced in order to produce a FET with the desired electrical characteristics.
Over the years, a substantial amount of research and development in the field semiconductor manufacturing has been dedicated to providing reduced thickness dielectric layers, as mentioned above. However, to be suitable for use as a MOSFET gate dielectric layer, these reduced thickness dielectric layers are typically required to have certain characteristics. For example, the dielectric layer should have a low density of interface states, a low density of defects, and a dielectric breakdown voltage high enough for use with the desired voltages that the MOSFET will encounter during operation.
What is needed is an extremely thin dielectric layer suitable for use as the gate dielectric layer in a MOSFET, and what is further needed are methods of making such a dielectric layer.
Briefly, a method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes passivating the surface of a semiconductor substrate at a temperature less than approximately 80xc2x0 C. and nitridizing the passivation layer.
In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have gate dielectric layers of a nitridized passivation layer.